SECURE HASH ALGORITHM IN DIGITAL HARDWARE FOR CRYPTOGRAPHIC APPLICATIONS

SECURE HASH ALGORITHM IN DIGITAL HARDWARE FOR CRYPTOGRAPHIC APPLICATIONS

Technology, implemented in digital hardware, software, or combination thereof, for completing Secure Hash Algorithm (SHA-2) computation with generating one new hash value at each clock cycle is described. The technology includes: using synchronous logic to store the computed values every alternate c...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Ganesan Gangesh Kumar, Agrawal Arvind
Format: Patent
Sprache:eng
Schlagworte:
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:Technology, implemented in digital hardware, software, or combination thereof, for completing Secure Hash Algorithm (SHA-2) computation with generating one new hash value at each clock cycle is described. The technology includes: using synchronous logic to store the computed values every alternate clock and combinational logic to process multiple rounds of SHA in each clock; completing hash calculation in unrolled modes; using efficient adders for most 32-bit adders to improve performance.