Enhanced Memory Device
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory cell configured to operate in multiple retention states including a static retention state and a dynamic retention state. The integrated circuit may include a controller config...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory cell configured to operate in multiple retention states including a static retention state and a dynamic retention state. The integrated circuit may include a controller configured to selectively apply different voltage levels to the memory cell based on the retention state of the memory cell. |
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