SYSTEM AND METHOD FOR RAM CAPACITY OPTIMIZATION USING ROM-BASED PAGING
Various embodiments of methods and systems for memory paging in a system on a chip ("SoC") are disclosed. An exemplary method includes identifying a subset of a baseline data image stored in a secondary storage device and determining that a revision data image requires an update of the sub...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | Various embodiments of methods and systems for memory paging in a system on a chip ("SoC") are disclosed. An exemplary method includes identifying a subset of a baseline data image stored in a secondary storage device and determining that a revision data image requires an update of the subset. In response to the update, generating a diff file that represents binary differences between the revision data image subset and the baseline data image subset. Next, storing the diff file in a primary storage device and, upon receiving a request for a data block associated with the revision data image that causes a page fault, generating the requested data block based on a combination of the baseline data image and the diff file. |
---|