WAFER LEVEL CHIP SCALE PACKAGE HAVING CONTINUOUS THROUGH HOLE VIA CONFIGURATION AND FABRICATION METHOD THEREOF

WAFER LEVEL CHIP SCALE PACKAGE HAVING CONTINUOUS THROUGH HOLE VIA CONFIGURATION AND FABRICATION METHOD THEREOF

A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Chung Kee-Wei, Chang Chia-Chang, Hsu Hung-Hsin, Lien Chia-Wen, Fang Li-Chih, Chang Wen-Hsiung
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.