METHOD AND SYSTEM FOR VERIFYING LAYOUT OF INTEGRATED CIRCUIT INCLUDING VERTICAL MEMORY CELLS

METHOD AND SYSTEM FOR VERIFYING LAYOUT OF INTEGRATED CIRCUIT INCLUDING VERTICAL MEMORY CELLS

A method and system for verifying a layout of an integrated circuit (IC) is disclosed. The IC may include a plurality of strings each including a plurality of memory cells which are vertically stacked on a substrate. The method may include receiving schematic data of the IC including instances of a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Lee Jae-eun, Kim Sung-hoon, Yang Hyang-ja, Son Jae-ick
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:A method and system for verifying a layout of an integrated circuit (IC) is disclosed. The IC may include a plurality of strings each including a plurality of memory cells which are vertically stacked on a substrate. The method may include receiving schematic data of the IC including instances of a string symbol and layout data, preparing a layout versus schematic (LVS) rule file in which a string device is defined, and performing LVS verification.