REDUCING ANTENNA EFFECTS IN SOI DEVICES

It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate diele...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Lorenz Ingolf, Hensel Ulrich, Block Stefan, Zier Michael, Narisetty Haritez, Faul Jürgen
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.