HIGH-SPEED RECEIVER ARCHITECTURE

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Agazzi Oscar Ernesto, Carrer Hugo Santiago, Luna German Cesar Augusto, Hueda Mario Rafael, Grace Carl, Crivelli Diego Ernesto
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.