LOW POWER VLSI DESIGNS USING CIRCUIT FAILURE IN SEQUENTIAL CELLS AS LOW VOLTAGE CHECK FOR LIMIT OF OPERATION

Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation of the design are provided. One such method involves the addition of a plurality of bits for sequential elements in the design including set of flip-flops, RAMs, ROMs and register files to add parity or single error correct and double error detect mechanism, a method to detect the parity errors or a single or double bit error in the sequential elements, starting at a nominal voltage of operation and gradually lowering the voltage setting till the first error is detected in the sequential elements, increasing the operating voltage by predetermined step above the voltage of first fail to achieve the optimal lowest voltage of correct operation of the design, storing this optimal voltage setting in a non-volatile memory for subsequent use.