DISTRIBUTED CONCATENATED ERROR CORRECTION

In one embodiment, a distributed concatenated error correction logic is disposed on separate integrated circuit dies to facilitate efficiency. In one embodiment, an inner error correction code logic of the distributed concatenated error correction logic is disposed on an integrated circuit die of a...

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Bibliographische Detailangaben
1. Verfasser:	MOTWANI Ravi H
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING CODE CONVERSION IN GENERAL CODING COMPUTING COUNTING DECODING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
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Beschreibung
Zusammenfassung:	In one embodiment, a distributed concatenated error correction logic is disposed on separate integrated circuit dies to facilitate efficiency. In one embodiment, an inner error correction code logic of the distributed concatenated error correction logic is disposed on an integrated circuit die of a memory circuit and an outer error correction code logic of the distributed concatenated error correction logic is disposed on an integrated circuit die of a memory controller. In one aspect, it is believed that such an arrangement may be employed to increase the usefulness of memory controllers for later generation memory circuits. Other aspects are described herein.