INTEGRATED TWO-TERMINAL DEVICE AND LOGIC DEVICE WITH COMPACT INTERCONNECTS HAVING SHALLOW VIA FOR EMBEDDED APPLICATION

Devices and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions and providing a plurality of interlevel dielectric (ILD) levels having tight pitch over the first and second regions of the substrate. An ILD level of which a two-terminal element disposed thereon corresponds to a first ILD level and its metal level corresponds to Mx, an immediate ILD level overlying the metal level Mx corresponds to a second ILD level includes via level Vx and metal level Mx+1 and the next overlying ILD level corresponds to a third ILD level includes via level Vx+1 and metal level Mx+2. The method includes forming a two-terminal device element is formed in between metal level Mx and via level Vx+1 in the first region.