HIGH SPEED FUNCTIONAL TEST VECTORS IN LOW POWER TEST CONDITIONS OF A DIGITAL INTEGRATED CIRCUIT

Implementations of the present disclosure involve an apparatus and/or method for conducting an at-speed functional test on a silicon wafer of an integrated circuit. In one embodiment, the method includes utilizing a first clock signal during a first portion of the test and a second clock signal during a second portion. The clock signals are configured such that a first subset of the logic stages of the circuit are tested at-speed by the first portion and a second subset of the logic stages of the circuit are tested at-speed. Further, in one embodiment, the first subset and the second subset comprise all of the logic stages of the circuit design. Through the configuration of the clock signals, the tester may ensure that each stage of the circuit design is tested at-speed such that a more accurate at-speed test result may be obtained in a low current environment.