Efficient Instruction Pair for Central Processing Unit (CPU) Instruction Design

A method implemented by a central processing unit (CPU), comprising decoding a first instruction word of a first instruction pair, wherein the first instruction word comprises a first operation code identifying a first operation, storing the first operation code in a register memory upon decoding the first instruction word, decoding a second instruction word of the first instruction pair, wherein the second instruction word comprises a first operand, generating a first decoded instruction pair by combining the first operation code stored in the register memory with the first operand in the second instruction word. The method further comprises executing the first decoded instruction pair by performing the first operation on the first operand.