POWER MULTIPLEXING WITH FLIP-FLOPS

Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing c...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	GEMAR Jeffrey, CAO Lipeng, VILANGUDIPITCHAI Ramaprasath
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.