PACKAGE STRUCTURE, CHIP STRUCTURE AND FABRICATION METHOD THEREOF

PACKAGE STRUCTURE, CHIP STRUCTURE AND FABRICATION METHOD THEREOF

A chip structure is provided, which includes: a substrate having a plurality of conductive pads formed on a surface thereof; a first copper layer formed on each of the conductive pads; a nickel layer formed on the first copper layer; a second copper layer formed on the nickel layer; and a tin layer...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Lu Chang-Lun, Tsai Jyun-Ling
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A chip structure is provided, which includes: a substrate having a plurality of conductive pads formed on a surface thereof; a first copper layer formed on each of the conductive pads; a nickel layer formed on the first copper layer; a second copper layer formed on the nickel layer; and a tin layer formed on the second copper layer, thereby effectively reducing stresses.