Method and Apparatus for Fabricating Wafer By Calculating Process Correction Parameters
A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Habets Boris |
| description | A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2017075230A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2017075230A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2017075230A13</originalsourceid><addsrcrecordid>eNqNi7EKwjAUALM4iPoPD5yFtEU612BxEQoqHcszfamBmISXdPDvFfQDnA6Ou6Xoz5QfYQT0IzQxImOeE5jA0OKdrcZs_QQ9GmI4vECh07P7yo6DppRABWbS2QYP3ed_UiZOa7Ew6BJtflyJbXu8qtOOYhgoRdTkKQ-3SymLWtb7spJNUf1XvQH7iDpw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and Apparatus for Fabricating Wafer By Calculating Process Correction Parameters</title><source>esp@cenet</source><creator>Habets Boris</creator><creatorcontrib>Habets Boris</creatorcontrib><description>A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.</description><language>eng</language><subject>APPARATUS SPECIALLY ADAPTED THEREFOR ; BASIC ELECTRIC ELEMENTS ; CINEMATOGRAPHY ; CONTROL OR REGULATING SYSTEMS IN GENERAL ; CONTROLLING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; ELECTROGRAPHY ; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS ; HOLOGRAPHY ; MATERIALS THEREFOR ; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS ; ORIGINALS THEREFOR ; PHOTOGRAPHY ; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES ; PHYSICS ; REGULATING ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170316&DB=EPODOC&CC=US&NR=2017075230A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170316&DB=EPODOC&CC=US&NR=2017075230A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Habets Boris</creatorcontrib><title>Method and Apparatus for Fabricating Wafer By Calculating Process Correction Parameters</title><description>A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.</description><subject>APPARATUS SPECIALLY ADAPTED THEREFOR</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CINEMATOGRAPHY</subject><subject>CONTROL OR REGULATING SYSTEMS IN GENERAL</subject><subject>CONTROLLING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>ELECTROGRAPHY</subject><subject>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</subject><subject>HOLOGRAPHY</subject><subject>MATERIALS THEREFOR</subject><subject>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</subject><subject>ORIGINALS THEREFOR</subject><subject>PHOTOGRAPHY</subject><subject>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</subject><subject>PHYSICS</subject><subject>REGULATING</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi7EKwjAUALM4iPoPD5yFtEU612BxEQoqHcszfamBmISXdPDvFfQDnA6Ou6Xoz5QfYQT0IzQxImOeE5jA0OKdrcZs_QQ9GmI4vECh07P7yo6DppRABWbS2QYP3ed_UiZOa7Ew6BJtflyJbXu8qtOOYhgoRdTkKQ-3SymLWtb7spJNUf1XvQH7iDpw</recordid><startdate>20170316</startdate><enddate>20170316</enddate><creator>Habets Boris</creator><scope>EVB</scope></search><sort><creationdate>20170316</creationdate><title>Method and Apparatus for Fabricating Wafer By Calculating Process Correction Parameters</title><author>Habets Boris</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2017075230A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>APPARATUS SPECIALLY ADAPTED THEREFOR</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CINEMATOGRAPHY</topic><topic>CONTROL OR REGULATING SYSTEMS IN GENERAL</topic><topic>CONTROLLING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>ELECTROGRAPHY</topic><topic>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</topic><topic>HOLOGRAPHY</topic><topic>MATERIALS THEREFOR</topic><topic>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</topic><topic>ORIGINALS THEREFOR</topic><topic>PHOTOGRAPHY</topic><topic>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</topic><topic>PHYSICS</topic><topic>REGULATING</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Habets Boris</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Habets Boris</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and Apparatus for Fabricating Wafer By Calculating Process Correction Parameters</title><date>2017-03-16</date><risdate>2017</risdate><abstract>A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2017075230A1 |
| source | esp@cenet |
| subjects | APPARATUS SPECIALLY ADAPTED THEREFOR BASIC ELECTRIC ELEMENTS CINEMATOGRAPHY CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROGRAPHY FUNCTIONAL ELEMENTS OF SUCH SYSTEMS HOLOGRAPHY MATERIALS THEREFOR MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS REGULATING SEMICONDUCTOR DEVICES |
| title | Method and Apparatus for Fabricating Wafer By Calculating Process Correction Parameters |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T13%3A46%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Habets%20Boris&rft.date=2017-03-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2017075230A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |