Method and Apparatus for Fabricating Wafer By Calculating Process Correction Parameters

A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated...

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Bibliographische Detailangaben
1. Verfasser:	Habets Boris
Format:	Patent
Sprache:	eng
Schlagworte:	APPARATUS SPECIALLY ADAPTED THEREFOR BASIC ELECTRIC ELEMENTS CINEMATOGRAPHY CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROGRAPHY FUNCTIONAL ELEMENTS OF SUCH SYSTEMS HOLOGRAPHY MATERIALS THEREFOR MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS REGULATING SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.