SYSTEM FOR OPTIMIZING POWER LEAKAGE AND TIMING DELAY IN AN INTEGRATED CIRCUIT BASED ON A COST FACTOR OF REPLACING CELLS

A method of and an apparatus for optimizing timing delay and power leakage in a circuit. The apparatus determines at least one path of a plurality of paths in a network of logic elements, the at least one path including a plurality of cells, each of the cells being configured to perform a logical operation. In addition, the apparatus identifies a first cell of the plurality of cells based on a first cost factor associated with replacing the first cell with a first replacement cell that performs the same logical operation, the first cost factor being a function of a power leakage difference and a timing delay difference associated with the first cell and the first replacement cell. Furthermore, the apparatus replaces the first cell with the first replacement cell in the at least one path.