CPU BIST TESTING OF INTEGRATED CIRCUITS USING SERIAL WIRE DEBUG

CPU BIST TESTING OF INTEGRATED CIRCUITS USING SERIAL WIRE DEBUG

A method of simultaneously built in self-testing (BIST) a sub circuit in a plurality of integrated circuit (IC) chips by embedded microprocessor (CPU) and SRAM memory using 2 to 4 digital pins per IC chip on automatic test equipment (ATE) using a serial wire debug testing protocol. A method of simul...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: Leung Nelson Kei
Format: Patent
Sprache:eng
Schlagworte:
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Beschreibung
Zusammenfassung:A method of simultaneously built in self-testing (BIST) a sub circuit in a plurality of integrated circuit (IC) chips by embedded microprocessor (CPU) and SRAM memory using 2 to 4 digital pins per IC chip on automatic test equipment (ATE) using a serial wire debug testing protocol. A method of simultaneously built in self-testing (BIST) an embedded nonvolatile memory in a plurality of integrated circuit (IC) chips by embedded microprocessor (CPU) and SRAM memory using 2 to 4 digital pins per IC chip on automatic test equipment (ATE) using a serial wire debug testing protocol.