Simulation of Hierarchical Circuit Element Arrays

This disclosure describes a design tool that iteratively performs simulation sets on an integrated circuit design, each corresponding to a different hierarchical level with each of the simulation sets producing a different set of simulation results. Each of the simulation sets utilizes a different set of local parameter values that include extreme instance local parameter values based on the set of simulation results of a preceding simulation set. The design tool generates a set of hierarchically aggregated simulation results based upon the last set of simulation results and global parameters, and modifies the integrated circuit design based upon a yield estimation that is determined from comparing the set of hierarchically aggregated simulation results to specification requirements that correspond to the integrated circuit design.