APPARATUS AND METHOD TO EMULATE A SEQUENCE OF INSTRUCTIONS VIA PARALLEL PROCESSORS

Instruction-execution processors each execute a first instruction. A control processor converts a second instruction to be emulated into the first instruction, and enters the converted first instruction into the instruction-execution processors. In a parallel-execution period, each instruction-execution processor executes a writing-access instruction or a reading-access instruction to a memory, suspends writing of data into the memory caused by the writing-access instruction, and retains an execution history of the writing-access instruction and the reading-access instruction. The control processor selects one of instruction-execution processors in which addresses of the memory access instructions conflict with each other, causes the selected instruction-execution processor to complete the writing of the data into the memory, enters first instructions to be executed in a next parallel-execution period into the selected instruction-execution processor, and causes another instruction-execution processor to re-execute first instructions executed by the other instruction-execution processors in the parallel-execution period, in the next parallel-execution period.