CMOS DEVICE INCLUDING A NON-STRAIGHT PN-BOUNDARY AND METHODS FOR GENERATING A LAYOUT OF A CMOS DEVICE
For each of two or more operating points, rise delays and fall delays associated with one or more clock cells are estimated. If the estimated rise delays and fall delays satisfy a given set of constraints, the layout of the CMOS device is accepted. Otherwise the layout is updated and a new analysis...
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| creator | Semenov Mikhail Yurievich Malashevich Denis Borisovich Kalashnikov Viacheslav Sergeyevich |
| description | For each of two or more operating points, rise delays and fall delays associated with one or more clock cells are estimated. If the estimated rise delays and fall delays satisfy a given set of constraints, the layout of the CMOS device is accepted. Otherwise the layout is updated and a new analysis round is performed. |
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If the estimated rise delays and fall delays satisfy a given set of constraints, the layout of the CMOS device is accepted. Otherwise the layout is updated and a new analysis round is performed.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170105&DB=EPODOC&CC=US&NR=2017004241A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76292</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170105&DB=EPODOC&CC=US&NR=2017004241A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Semenov Mikhail Yurievich</creatorcontrib><creatorcontrib>Malashevich Denis Borisovich</creatorcontrib><creatorcontrib>Kalashnikov Viacheslav Sergeyevich</creatorcontrib><title>CMOS DEVICE INCLUDING A NON-STRAIGHT PN-BOUNDARY AND METHODS FOR GENERATING A LAYOUT OF A CMOS DEVICE</title><description>For each of two or more operating points, rise delays and fall delays associated with one or more clock cells are estimated. If the estimated rise delays and fall delays satisfy a given set of constraints, the layout of the CMOS device is accepted. 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| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
| title | CMOS DEVICE INCLUDING A NON-STRAIGHT PN-BOUNDARY AND METHODS FOR GENERATING A LAYOUT OF A CMOS DEVICE |
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