CMOS DEVICE INCLUDING A NON-STRAIGHT PN-BOUNDARY AND METHODS FOR GENERATING A LAYOUT OF A CMOS DEVICE

CMOS DEVICE INCLUDING A NON-STRAIGHT PN-BOUNDARY AND METHODS FOR GENERATING A LAYOUT OF A CMOS DEVICE

For each of two or more operating points, rise delays and fall delays associated with one or more clock cells are estimated. If the estimated rise delays and fall delays satisfy a given set of constraints, the layout of the CMOS device is accepted. Otherwise the layout is updated and a new analysis...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Semenov Mikhail Yurievich, Malashevich Denis Borisovich, Kalashnikov Viacheslav Sergeyevich
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:For each of two or more operating points, rise delays and fall delays associated with one or more clock cells are estimated. If the estimated rise delays and fall delays satisfy a given set of constraints, the layout of the CMOS device is accepted. Otherwise the layout is updated and a new analysis round is performed.