Method and Apparatus for Reducing SAR Input Loading

The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an array of MSB (most significant bit) capacitors, an array of LSB (least significant bit) capacitors, and an error correction capacitor. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A successive approximation register (SAR) state machine is coupled to the zero crossing detector and operates the charge sharing DAC in a sampling mode and a conversion mode. During the sampling mode an input voltage is provided to the array of MSB capacitors and the error correction capacitor.