MEMORY SYSTEMS HAVING REDUCED MEMORY CHANNEL TRAFFIC AND METHODS FOR OPERATING THE SAME

A memory device controller includes an error correction processor and a compression processor. The error correction processor is configured to obtain error location information for page data received from a source memory block over a memory channel. The compression processor is configured to compres...

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Bibliographische Detailangaben
Hauptverfasser: BERMAN Amit, KONG Jun Jin, BEITLER Uri
Format: Patent
Sprache:eng
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Zusammenfassung:A memory device controller includes an error correction processor and a compression processor. The error correction processor is configured to obtain error location information for page data received from a source memory block over a memory channel. The compression processor is configured to compress the obtained error location information, and to output the compressed error location information to a target memory block without the page data over the same memory channel.