MEMORY MANAGEMENT

A multiple stage memory management unit (MMU) comprises a first MMU stage configured to translate an input virtual memory address to a corresponding intermediate memory address, the first MMU stage generating a set of two or more intermediate memory addresses including the corresponding intermediate...

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Bibliographische Detailangaben
Hauptverfasser:	TER-GRIGORYAN Vahan, PERSSON Hakan Lars-Goran, PAI Vinod Pisharath Hari, de los REYES DARIAS Jesus Javier
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS PHYSICS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE
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Beschreibung
Zusammenfassung:	A multiple stage memory management unit (MMU) comprises a first MMU stage configured to translate an input virtual memory address to a corresponding intermediate memory address, the first MMU stage generating a set of two or more intermediate memory addresses including the corresponding intermediate memory address; and a second MMU stage configured to translate an intermediate memory address provided by the first MMU stage to a physical memory address, the second MMU stage providing, in response to an intermediate memory address received from the first MMU stage, a set of two or more physical memory addresses including the physical memory address corresponding to the intermediate memory address received from the first MMU stage; the first MMU stage being configured to provide to the second MMU stage for translation, intermediate memory addresses in the set other than any intermediate memory addresses in the set for which the second MMU stage will provide a physical memory address as a response to translation of one of the other intermediate memory addresses in the set.