METHODS AND DEVICES FOR DETERMINING LOGICAL TO PHYSICAL MAPPING ON AN INTEGRATED CIRCUIT

Devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment includes a die which has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have intentionally induced defects that form a p...

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Bibliographische Detailangaben
Hauptverfasser:	Prinslow Douglas A, Ashburn Stanton Petree, Kasper Abha Singh, Plumton Donald L, Waite Harold C, Rullan Eric D, Corum, JR. Daniel L
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES STATIC STORES TESTING
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Beschreibung
Zusammenfassung:	Devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment includes a die which has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have intentionally induced defects that form a predetermined fault pattern.