Apparatus and Method for Reducing Latency Between Host and a Storage Device
Described is a system comprising: a storage device; a bus; and a host apparatus including a host memory and a driver module, wherein the host apparatus is coupled to the storage device via the bus, wherein the driver module is operable to: retrieve a logical to physical address mapping from the host...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | Described is a system comprising: a storage device; a bus; and a host apparatus including a host memory and a driver module, wherein the host apparatus is coupled to the storage device via the bus, wherein the driver module is operable to: retrieve a logical to physical address mapping from the host memory; and provide the logical to physical address mapping to the storage device via the bus along with a read or write operation request. Described is a method comprising: retrieving a logical to physical address mapping from a host memory; and providing the logical to physical address mapping to a storage device via a bus along with a read or write operation request. Described is a machine readable storage medium having instructions stored thereon that, when executed, cause a machine to perform the method described above. |
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