INTEGRATED ENHANCEMENT MODE AND DEPLETION MODE DEVICE STRUCTURE AND METHOD OF MAKING THE SAME

INTEGRATED ENHANCEMENT MODE AND DEPLETION MODE DEVICE STRUCTURE AND METHOD OF MAKING THE SAME

A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided...

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Bibliographische Detailangaben
Hauptverfasser: NECHAY BETTINA, CRAMER HARLAN CARL, PARKE JUSTIN ANDREW, HOWELL ROBERT S, HENRY HOWELL GEORGE, STEWART ERIC J, GUPTA SHALINI, KING MATTHEW RUSSELL, FREITAG RONALD G, RENALDO KAREN MARIE
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.