METAL LINE CONNECTION FOR IMPROVED RRAM RELIABILITY, SEMICONDUCTOR ARRANGEMENT COMPRISING THE SAME, AND MANUFACTURE THEREOF

METAL LINE CONNECTION FOR IMPROVED RRAM RELIABILITY, SEMICONDUCTOR ARRANGEMENT COMPRISING THE SAME, AND MANUFACTURE THEREOF

Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: HUANG KUOING, TSAI CHUN-YANG, TING YU-WEI
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.