LOW VOLTAGE SRAM

LOW VOLTAGE SRAM

In some embodiments, an SRAM includes an array of storage cells arranged as rows and columns, each storage cell of the array of storage cells includes a first type of transistor and a second type of transistor. The SRAM also includes a memory controller configured to detect a temperature of the SRAM...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SEETHARAMAN PREMKUMAR, MENEZES VINOD
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:In some embodiments, an SRAM includes an array of storage cells arranged as rows and columns, each storage cell of the array of storage cells includes a first type of transistor and a second type of transistor. The SRAM also includes a memory controller configured to detect a temperature of the SRAM and apply a body bias to the first type of transistor in each of the storage cells and refrain from an application of a body bias to the second type of transistor in each of the storage cells.