Metallization stack and chip arrangement

A metallization stack for a chip arrangement is provided, wherein the metallization stack comprises a first metallic layer; a plating layer comprising an alloy comprising nickel and zinc arranged over the first metallic structure; and a second metallic layer arranged over the plating layer.

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Bibliographische Detailangaben
1. Verfasser:	LEE SWEE KAH
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY LAYERED PRODUCTS LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM PERFORMING OPERATIONS SEMICONDUCTOR DEVICES TRANSPORTING
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Beschreibung
Zusammenfassung:	A metallization stack for a chip arrangement is provided, wherein the metallization stack comprises a first metallic layer; a plating layer comprising an alloy comprising nickel and zinc arranged over the first metallic structure; and a second metallic layer arranged over the plating layer.