SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas...

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Bibliographische Detailangaben
Hauptverfasser: NEIGER GILBERT, UHLIG RICHARD, RODGERS SCOTT DION, RUST CAMRON, BENNETT STEVEN M, SANKARAN RAJESH M, SCHOENBERG SEBASTIAN, ANDERSON ANDREW V
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.