SEMICONDUCTOR MEMORY DEVICE

A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting one of the memory blocks and a control signal for causi...

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Bibliographische Detailangaben
Hauptverfasser: HOSONO KOJI, KUROSAWA TOMONORI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting another one of the memory blocks.