TIME-TO-DIGITAL CONVERTER

A time-to-digital converter (TDC) in which a chain of inverters with finite propagation delays form a delay line in which a level transition applied to one end of the delay line from an input line produces a series of progressively delayed level transitions of alternating polarity along the delay line. Each inverter has an associated pass gate, with the output of the inverter together with the output of the preceding delay line element driving the complementary gate inputs of the pass gate. The complementary gate inputs of each pass gate are coupled to the corresponding delay line outputs in an alternating manner so that, as the level transitions traverse the delay line, the pass gates are progressively enabled to couple the input line to corresponding output lines to produce a series of progressively delayed level transitions of like polarity on those output lines.