METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE SELECTIVE REMOVAL OF SUCH FINS
One method includes forming a plurality of first trenches in a semiconductor substrate to thereby define a plurality of initial fins in the substrate, removing at least one, but less than all, of the plurality of initial fins, forming a fin protection layer on at least the sidewalls of the remaining...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | XIE RUILONG WEI ANDY C |
description | One method includes forming a plurality of first trenches in a semiconductor substrate to thereby define a plurality of initial fins in the substrate, removing at least one, but less than all, of the plurality of initial fins, forming a fin protection layer on at least the sidewalls of the remaining initial fins, with the fin protection layer in position, performing an etching process to extend a depth of the first trenches to thereby define a plurality of final trenches with a final trench depth, wherein the final trenches define a plurality of final fin structures that each comprise an initial fin, removing the fin protection layer, and forming a recessed layer of insulating material in the final trenches, wherein the recessed layer of insulating material has a recessed surface that exposes a portion of the final fin structures. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2015279971A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2015279971A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2015279971A13</originalsourceid><addsrcrecordid>eNqNjLsKwjAUhrs4iPoOBzoLpiKlY0hOTKBJoLmsoUicRAv1_TERH8Dpv_Jtm6TRS8sdWAHCTlqZKwhlXA3VCPTgUCtmDQ_Ml5JjVAwdUMPBSyzriMyriDChtpGOFeUCk1_Ovtnc58eaDz_dNW1BMnnMyyvldZlv-ZnfKbjuRC5dPww9oeT83-sD-Zwz5g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE SELECTIVE REMOVAL OF SUCH FINS</title><source>esp@cenet</source><creator>XIE RUILONG ; WEI ANDY C</creator><creatorcontrib>XIE RUILONG ; WEI ANDY C</creatorcontrib><description>One method includes forming a plurality of first trenches in a semiconductor substrate to thereby define a plurality of initial fins in the substrate, removing at least one, but less than all, of the plurality of initial fins, forming a fin protection layer on at least the sidewalls of the remaining initial fins, with the fin protection layer in position, performing an etching process to extend a depth of the first trenches to thereby define a plurality of final trenches with a final trench depth, wherein the final trenches define a plurality of final fin structures that each comprise an initial fin, removing the fin protection layer, and forming a recessed layer of insulating material in the final trenches, wherein the recessed layer of insulating material has a recessed surface that exposes a portion of the final fin structures.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20151001&DB=EPODOC&CC=US&NR=2015279971A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20151001&DB=EPODOC&CC=US&NR=2015279971A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>XIE RUILONG</creatorcontrib><creatorcontrib>WEI ANDY C</creatorcontrib><title>METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE SELECTIVE REMOVAL OF SUCH FINS</title><description>One method includes forming a plurality of first trenches in a semiconductor substrate to thereby define a plurality of initial fins in the substrate, removing at least one, but less than all, of the plurality of initial fins, forming a fin protection layer on at least the sidewalls of the remaining initial fins, with the fin protection layer in position, performing an etching process to extend a depth of the first trenches to thereby define a plurality of final trenches with a final trench depth, wherein the final trenches define a plurality of final fin structures that each comprise an initial fin, removing the fin protection layer, and forming a recessed layer of insulating material in the final trenches, wherein the recessed layer of insulating material has a recessed surface that exposes a portion of the final fin structures.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLsKwjAUhrs4iPoOBzoLpiKlY0hOTKBJoLmsoUicRAv1_TERH8Dpv_Jtm6TRS8sdWAHCTlqZKwhlXA3VCPTgUCtmDQ_Ml5JjVAwdUMPBSyzriMyriDChtpGOFeUCk1_Ovtnc58eaDz_dNW1BMnnMyyvldZlv-ZnfKbjuRC5dPww9oeT83-sD-Zwz5g</recordid><startdate>20151001</startdate><enddate>20151001</enddate><creator>XIE RUILONG</creator><creator>WEI ANDY C</creator><scope>EVB</scope></search><sort><creationdate>20151001</creationdate><title>METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE SELECTIVE REMOVAL OF SUCH FINS</title><author>XIE RUILONG ; WEI ANDY C</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2015279971A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>XIE RUILONG</creatorcontrib><creatorcontrib>WEI ANDY C</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>XIE RUILONG</au><au>WEI ANDY C</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE SELECTIVE REMOVAL OF SUCH FINS</title><date>2015-10-01</date><risdate>2015</risdate><abstract>One method includes forming a plurality of first trenches in a semiconductor substrate to thereby define a plurality of initial fins in the substrate, removing at least one, but less than all, of the plurality of initial fins, forming a fin protection layer on at least the sidewalls of the remaining initial fins, with the fin protection layer in position, performing an etching process to extend a depth of the first trenches to thereby define a plurality of final trenches with a final trench depth, wherein the final trenches define a plurality of final fin structures that each comprise an initial fin, removing the fin protection layer, and forming a recessed layer of insulating material in the final trenches, wherein the recessed layer of insulating material has a recessed surface that exposes a portion of the final fin structures.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2015279971A1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE SELECTIVE REMOVAL OF SUCH FINS |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-22T00%3A27%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=XIE%20RUILONG&rft.date=2015-10-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2015279971A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |