Selecting A Low Power State Based On Cache Flush Latency Determination

Selecting A Low Power State Based On Cache Flush Latency Determination

In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache b...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: DURG AJAYA V, RAMANI SUNDAR, CHOUBAL ASHISH V, MANDHANI ARVIND, CHAKKI SAMUDYATHA, RAMAN ARVIND, MUTHUKUMAR KALYAN
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.