PARTITIONED ERROR CODE COMPUTATION

A circuit provides parallel computation of error codes for simultaneously received words. The words received simultaneously may be portions of a common data message, or may be portions of distinct data messages. Accordingly, the circuit selectively accumulates the error codes based on their association with successive data words, outputting an accumulated error code when the last word of a data message has been received and the respective error code is calculated. Based on such information, the error codes calculated in parallel can be output independently, accumulated with one another, or accumulated with the error codes of a previous or subsequent calculation cycle. Thus, the circuit dynamically provides a single parallel error code generation of a given width or multiple parallel error code generations, each of a width divisible by the given width.