QUICK COMPARISON CIRCUIT
A quick comparison circuit includes a cascaded N-stage operational amplifier, a flip-latch, a biasing circuit, and a control signal generating circuit, with N 2, and two differential signals to be compared being inputted to an input terminal of a first stage operational amplifier, an output terminal...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | A quick comparison circuit includes a cascaded N-stage operational amplifier, a flip-latch, a biasing circuit, and a control signal generating circuit, with N 2, and two differential signals to be compared being inputted to an input terminal of a first stage operational amplifier, an output terminal of a Nth stage operational amplifier being connected with an input terminal of the flip-latch, the biasing circuit supplying a biasing current to each stage operational amplifier, the control signal generating circuit being connected with the N-stage operational amplifier and the flip-latch respectively to supply a working time sequence and a reset control signal for them, and each stage operational amplifier having the same structure. This circuit has high gain and improved comparison speed. |
---|