CHIP STACK WITH ELECTRICALLY INSULATING WALLS

CHIP STACK WITH ELECTRICALLY INSULATING WALLS

A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads.

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: NAH JAE-WOONG, COLGAN EVAN G
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads.