CACHE MEMORY DATA COMPRESSION AND DECOMPRESSION

A cache memory data compression and decompression technique is described. A processor device includes a memory controller unit (MCU) coupled to a main memory and a cache memory. The MCU includes a cache memory data compression and decompression module that compresses data received from the main memo...

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Bibliographische Detailangaben
Hauptverfasser:	AGUILAR ARREOLA MANUEL A, MARRUGO MARGARETH E, ALAMELDEEN ALAA R, PUDAR STEVEN D, BALLAPURAM CHINNAKRISHNAN, COORAY NIRANJAN L, GAUR JAYESH
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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Beschreibung
Zusammenfassung:	A cache memory data compression and decompression technique is described. A processor device includes a memory controller unit (MCU) coupled to a main memory and a cache memory. The MCU includes a cache memory data compression and decompression module that compresses data received from the main memory. The compressed data may then be stored in the cache memory. The cache memory data compression and decompression module may also decompress data that is stored in the cache memory. For example, in response to a cache hit for data requested by a processor, the compressed data in the cache memory may be decompressed and subsequently read or operated upon by the processor.