CONTENTION MANAGEMENT FOR A HARDWARE TRANSACTIONAL MEMORY

CONTENTION MANAGEMENT FOR A HARDWARE TRANSACTIONAL MEMORY

A hardware transactional memory is provided within a multiprocessor system with coherency control and hardware transaction memory control circuitry that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes pre...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BLAKE GEOFFREY, BILES STUART DAVID, CHONG NATHAN YONG SENG, ÖZER EMRE, DRESLINSKI RONALD GEORGE, MUDGE TREVOR NIGEL
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A hardware transactional memory is provided within a multiprocessor system with coherency control and hardware transaction memory control circuitry that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.