LINE LAYOUT FOR SEMICONDUCTOR MEMORY APPARATUS

LINE LAYOUT FOR SEMICONDUCTOR MEMORY APPARATUS

Provided is a line layout for a semiconductor memory apparatus, which is a line layout of a line layer formed over a memory region so as to cross the memory region. The line layout includes as unit lines: a data line disposed between a pair of shielding lines; a pair of address line groups disposed...

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1. Verfasser: LEE SEOL HEE
Format: Patent
Sprache:eng
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Zusammenfassung:Provided is a line layout for a semiconductor memory apparatus, which is a line layout of a line layer formed over a memory region so as to cross the memory region. The line layout includes as unit lines: a data line disposed between a pair of shielding lines; a pair of address line groups disposed at one side of the shielding lines; and a power supply line disposed between the pair of address line groups.