SELF-BIASED DELAY LOCKED LOOP WITH DELAY LINEARIZATION

Apparatuses and methods for a self-biased delay looked loop with delay linearization are provided. One example delay locked loop (DU) circuit (100, 200) can include a digital-to-analog converter (DAC) (104, 204, 304) and a bias generator (188, 208) communicatively coupled to an output of the DAC (106, 206, 306). The bias generator (108, 206) is configured to provide a clock signal and a bias signal. A delay control circuit (DCC) (109, 209) is communicatively coupled to the bias generator (108, 208). The DCC (109, 209) is configured to provide a delayed clock signal based on the clock signal and the bias signal. A DAC bias circuit (122, 222, 422) is communicatively coupled to the DAC (106, 206, 306) and configured to provide a feedback signal to the DAC (104, 204, 304) based on the bias signal. The DAC bias circuit (122, 222, 422) configured to adjust the feedback signal to cause the delayed clock signal at the output of the DAC (106, 206, 306) to be non-linear to counteract non-linear delay characteristics of the DCC (109, 209).