BUMPLESS BUILD-UP LAYER PACKAGE WARPAGE REDUCTION

BUMPLESS BUILD-UP LAYER PACKAGE WARPAGE REDUCTION

The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MALATKAR PRAMOD, DELANEY DREW W
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.