METHOD AND PROCESS TO REDUCE STRESS BASED OVERLAY ERROR

Thermal processing and alignment methods and processes used during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device after at least one laser annealing process is completed, the device including a substrate surface and at least one layer over the substrate surface; applying a mask layer to the at least one layer; performing lithography on the mask layer to form a top layer; positioning a first contact-to-gate layer over the top layer; checking alignment of electrical connections between the substrate surface and the first contact-to-gate layer; and determining if an adjustment is needed to at least one parameter of at least one laser annealing beam used during the laser annealing process. In enhanced aspects, the at least one laser annealing process includes: performing three laser anneals; applying three mask layers; and performing lithography three times.