SEMICONDUCTOR TEST METHOD AND SEMICONDUCTOR TEST APPARATUS

SEMICONDUCTOR TEST METHOD AND SEMICONDUCTOR TEST APPARATUS

A semiconductor test method includes attaching a sheet to a wafer on which a plurality of chips are formed, the sheet having a plurality of holes, each of which corresponds to a position of one of the chips, dicing the wafer to separate the plurality of chips into individual chips while the sheet re...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MORINO KEIJI, MIKI KENICHI
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MORINO KEIJI
MIKI KENICHI
description A semiconductor test method includes attaching a sheet to a wafer on which a plurality of chips are formed, the sheet having a plurality of holes, each of which corresponds to a position of one of the chips, dicing the wafer to separate the plurality of chips into individual chips while the sheet remains attached to the individual chips, and after the dicing and while the sheet remains attached to the individual chips, measuring the electrical characteristics of the chips.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2014342475A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2014342475A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2014342475A13</originalsourceid><addsrcrecordid>eNrjZLAKdvX1dPb3cwl1DvEPUghxDQ5R8HUN8fB3UXD0c1HAIusYEOAY5BgSGszDwJqWmFOcyguluRmU3VxDnD10Uwvy41OLCxKTU_NSS-JDg40MDE2MTYxMzE0dDY2JUwUAh04qWA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR TEST METHOD AND SEMICONDUCTOR TEST APPARATUS</title><source>esp@cenet</source><creator>MORINO KEIJI ; MIKI KENICHI</creator><creatorcontrib>MORINO KEIJI ; MIKI KENICHI</creatorcontrib><description>A semiconductor test method includes attaching a sheet to a wafer on which a plurality of chips are formed, the sheet having a plurality of holes, each of which corresponds to a position of one of the chips, dicing the wafer to separate the plurality of chips into individual chips while the sheet remains attached to the individual chips, and after the dicing and while the sheet remains attached to the individual chips, measuring the electrical characteristics of the chips.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20141120&amp;DB=EPODOC&amp;CC=US&amp;NR=2014342475A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20141120&amp;DB=EPODOC&amp;CC=US&amp;NR=2014342475A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MORINO KEIJI</creatorcontrib><creatorcontrib>MIKI KENICHI</creatorcontrib><title>SEMICONDUCTOR TEST METHOD AND SEMICONDUCTOR TEST APPARATUS</title><description>A semiconductor test method includes attaching a sheet to a wafer on which a plurality of chips are formed, the sheet having a plurality of holes, each of which corresponds to a position of one of the chips, dicing the wafer to separate the plurality of chips into individual chips while the sheet remains attached to the individual chips, and after the dicing and while the sheet remains attached to the individual chips, measuring the electrical characteristics of the chips.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAKdvX1dPb3cwl1DvEPUghxDQ5R8HUN8fB3UXD0c1HAIusYEOAY5BgSGszDwJqWmFOcyguluRmU3VxDnD10Uwvy41OLCxKTU_NSS-JDg40MDE2MTYxMzE0dDY2JUwUAh04qWA</recordid><startdate>20141120</startdate><enddate>20141120</enddate><creator>MORINO KEIJI</creator><creator>MIKI KENICHI</creator><scope>EVB</scope></search><sort><creationdate>20141120</creationdate><title>SEMICONDUCTOR TEST METHOD AND SEMICONDUCTOR TEST APPARATUS</title><author>MORINO KEIJI ; MIKI KENICHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2014342475A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>MORINO KEIJI</creatorcontrib><creatorcontrib>MIKI KENICHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MORINO KEIJI</au><au>MIKI KENICHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR TEST METHOD AND SEMICONDUCTOR TEST APPARATUS</title><date>2014-11-20</date><risdate>2014</risdate><abstract>A semiconductor test method includes attaching a sheet to a wafer on which a plurality of chips are formed, the sheet having a plurality of holes, each of which corresponds to a position of one of the chips, dicing the wafer to separate the plurality of chips into individual chips while the sheet remains attached to the individual chips, and after the dicing and while the sheet remains attached to the individual chips, measuring the electrical characteristics of the chips.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2014342475A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
title SEMICONDUCTOR TEST METHOD AND SEMICONDUCTOR TEST APPARATUS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-19T06%3A50%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MORINO%20KEIJI&rft.date=2014-11-20&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2014342475A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true