HARDWARE UNIT FOR FAST SAH-OPTIMIZED BVH CONSTRUTION

A graphics data processing architecture is disclosed for constructing a hierarchically-ordered acceleration data structure in a rendering process. The architecture includes at least first and second builder modules, connected to one another and respectively configured for building a plurality of upper and lower hierarchical levels of the data structure. Each builder module comprises at least one memory interface with at least a pair of memories; at least two partitioning units, each connected to one respective of the pairs of memories; at least three binning units connected with each partitioning unit and the memory interface, one binning unit for each of the threes axes X, Y and Z of a three-dimensional graphics scene; and a plurality of calculating modules connected with the binning units for calculating a computing cost associated with each of a plurality of splits from a splitting plane and for outputting data representative of a lowest cost split.