TEST APPARATUS AND TEST SYSTEM

A test apparatus of the present embodiment has a logic cell, a host and a first bus. The host includes: a conversion section configured to analyze a test vector and convert the test vector to signal control data and a waveform shape; and a judgment section configured to analyze an expected value comparison result to perform success/failure judgment of a test of a semiconductor circuit. The logic cell is provided with a first storage section configured to store the signal control data, a second storage section configured to store the waveform shape as a waveform shape table, a waveform generating section configured to generate an output waveform for controlling the semiconductor circuit and output the output waveform, and an expected value comparing section configured to obtain the expected value comparison result on the basis of the signal control data and the waveform shape table.