Efficient Hardware Structure For Sorting/Adding Multiple Inputs Assigned To Different Bins

In one embodiment, a four-input, four-output bin adder is disclosed. The bin adder comprises a two-by-three, multi-stage, cascaded array of two-input, two-output adder circuits. Each of the bin-adder input signals comprises a numeric data value and an associated address, and the bin adder is adapted...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SHAFFER MICHAEL S, YOON WON J, CARGILLE DAVID L, MANZELLA JOSEPH A
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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