Efficient Hardware Structure For Sorting/Adding Multiple Inputs Assigned To Different Bins

In one embodiment, a four-input, four-output bin adder is disclosed. The bin adder comprises a two-by-three, multi-stage, cascaded array of two-input, two-output adder circuits. Each of the bin-adder input signals comprises a numeric data value and an associated address, and the bin adder is adapted to add together (a.k.a. accumulate) the numeric values of only those inputs signals having addresses that are the same. In particular, the inputs and outputs of the two-input, two-output adder circuits are connected together in such a way that each input signal is compared to every other input signal, in a round-robin configuration. If the associated addresses match, then the input signals' numeric data values are added (i.e., accumulated) and output as a single signal comprising the sum of the numeric data values and the common address.